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| Page Title | Mentor Graphics 10 Gigabit BASE-R Physical Coding Sublayer IP Core |
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| Description | The M-XGPCSR module from the Mentor Graphics Corporation implements the IEEE 803ae Clause 49 10-Gigabit PCS-R function. This function is located between the reconciliation sublayer (RS) and the PMA sublayer. The M-XGPCSR connects to the RS side (MAC) with a 36-bit DDR interface or a 72-bit SDR interface for both Tx and Rx. On the PMA side, it connects with either the 16-bit (XSBI) interface or a 64-bit SDR interface for both Tx and Rx. The M-XGPCSR also implements Clause 45 to provide control and status through the management data input/output (MDIO) interface. The M-XGPCSR is written in Verilog RTL and comes with a stand alone verification environment. In addition, synthesis scripts are supplied for TSMC 0.13um ASIC library and Altera StratixII FPGA. These scripts can easily be adapted to other technologies. |
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| Hyperlink | http://www.design-reuse.com/login2.php?n … =sip&productid=10119 |
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| 20 more pages from the same domain ( www.design-reuse.com) are linked |
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| Linked From |   RS - Reconciliation Sublayer
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| Suggested | 1/23/2009 8:19:00 PM |
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| Updated | 1/23/2009 8:19:00 PM |
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